This invention relates to programmable logic device (“PLD”) integrated circuits and other devices of that general type (all referred to generically herein as PLDs). More particularly, the invention relates to systems and methods for mapping logic functions into synchronous embedded memory blocks (“EMBs”) of a PLD.
PLDs are typically made up of I/O resources, interconnect resources, logic resources, and memory resources. PLDs may also contain other resources, such as digital signal processing blocks (“DSPs”) and other embedded processing resources. The logic resources typically include logic elements (“LEs”) grouped in clusters that are sometimes referred to as logic array blocks (“LABs”). The memory resources typically include EMBs of various sizes.
Modern PLDs include an increasing number of EMBs that may be used as on-chip memories. While there are some applications that that make use of this on-chip memory, the area devoted to the EMBs may be wasted when applications do not utilize this built in memory.
One solution to this problem is to use unutilized EMBs as a read only memory (“ROM”) that is capable of implementing multi-input multi-output logic functions. A truth table containing all of the potential input signals of a particular logic function and their associated output functions may be stored in a ROM. Thus, logic that would traditionally be mapped into LEs may instead be placed into unused EMBs. This technique may increase the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement the particular circuit.
Earlier use of fully asynchronous or switchable asynchronous/synchronous memories in PLDs has largely shifted to fully synchronous memories. There are several notable differences between synchronous memories and their traditional asynchronous counterparts. Most importantly, synchronous memories require all read and write operations to be synchronized to a clock edge. In contrast, asynchronous memories may perform read and write operations independent of a clock signal.
Instead of relying on a clock signal, asynchronous memories have strict timing constraints regarding setup and hold times for address and data lines before writing or reading may be enabled. Synchronous memories avoid these complications as the designer need only ensure that the address, data, and control signals reach the memory interface before the next active clock edge. The synchronous memory block automatically generates internal control signals that are designed to meet these setup and hold constraints. Simpler timing and potential for power savings have made synchronous EMBs increasingly popular in modern PLDs.
Various techniques for mapping combinational logic clusters into EMBs have been considered. However, these techniques cannot be used to map logic into the synchronous EMBs present in modern PLDs.